{"id":5265,"date":"2023-07-14T06:29:46","date_gmt":"2023-07-14T06:29:46","guid":{"rendered":"https:\/\/www.synsense.ai\/?p=5265"},"modified":"2023-08-02T06:31:52","modified_gmt":"2023-08-02T06:31:52","slug":"async2023-kicks-off-novel-ideas-in-asynchronous-circuitry-new-applications-and-fresh-directions-ahead","status":"publish","type":"post","link":"https:\/\/www.synsense.ai\/zh-hans\/async2023-kicks-off-novel-ideas-in-asynchronous-circuitry-new-applications-and-fresh-directions-ahead\/","title":{"rendered":"ASYNC2023\u5373\u5c06\u5f00\u5e55, \u5f02\u6b65\u7535\u8def&\u7c7b\u8111\u65b0\u60f3\u6cd5\/\u65b0\u5e94\u7528\/\u65b0\u98ce\u5411\u524d\u77bb!"},"content":{"rendered":"

\u7b2c28\u5c4aIEEE\u5f02\u6b65\u7535\u8def\u4e0e\u7cfb\u7edf\u56fd\u9645\u4f1a\u8bae\uff08ASYNC<\/a>\uff09\u5373\u5c06\u4e8e7\u670816\u65e5\u81f319\u65e5\u5728\u4e2d\u56fd\u5317\u4eac\u4e3e\u884c\u3002\u8fd9\u662f\u4f1a\u8bae\u9996\u6b21\u843d\u5730\u4e2d\u56fd\uff0c\u7531\u6e05\u534e\u5927\u5b66\u4e3b\u529e\uff0cSynSense\u65f6\u8bc6\u79d1\u6280<\/a>\u53ca\u5317\u4eac\u4fe1\u606f\u79d1\u5b66\u4e0e\u6280\u672f\u56fd\u5bb6\u7814\u7a76\u4e2d\u5fc3\u652f\u6301\uff0c\u65e8\u5728\u4e3a\u6765\u81ea\u5b66\u672f\u754c\u548c\u5de5\u4e1a\u754c\u7684\u7814\u7a76\u4eba\u5458\u548c\u5de5\u7a0b\u5e08\u63d0\u4f9b\u9ad8\u8d28\u91cf\u7684\u56fd\u9645\u8bba\u575b\uff0c\u5c55\u793a\u5168\u7403\u5f02\u6b65VLSI\u8bbe\u8ba1\u7684\u6700\u65b0\u89c1\u89e3\u548c\u6210\u679c\u3002<\/p>\n

\u672c\u6b21\u5927\u4f1a\u4e2d\uff0cSynSense\u65f6\u8bc6\u79d1\u6280\u8054\u5408\u521b\u59cb\u4eba\u3001\u82cf\u9ece\u4e16\u5927\u5b66\/\u82cf\u9ece\u4e16\u8054\u90a6\u7406\u5de5Giacomo Indiveri\u6559\u6388\u5c06\u62c5\u4efb\u5f00\u5e55\u5f0f\u4e3b\u8bb2\u5609\u5bbe\uff0cSynSense\u65f6\u8bc6\u79d1\u6280\u521b\u59cb\u4eba\u517cCEO\u4e54\u5b81\u535a\u58eb\u62c5\u4efb\u5de5\u4e1a\u8054\u7edc\u4e3b\u5e2d\uff0cSynSense\u65f6\u8bc6\u79d1\u6280\u6280\u672f\u56e2\u961f\u5c06\u8bb2\u89e3\u7eaf\u5f02\u6b65\u7535\u8def\u8bbe\u8ba1\u7684\u5168\u7403\u9996\u6b3e\u611f\u7b97\u4e00\u4f53\u52a8\u6001\u89c6\u89c9SoC Speck\u2122<\/a><\/strong>\u5e76\u5c55\u793a\u6700\u65b0\u52a8\u6001\u89c6\u89c9demo\u3002<\/p>\n

\u4ee5\u4e8b\u4ef6\u9a71\u52a8\u3001\u4f4e\u529f\u8017\u53ca\u9ad8\u80fd\u6548\u4e3a\u7279\u70b9\uff0c\u5f02\u6b65\u8bbe\u8ba1\u5728\u5927\u89c4\u6a21\u5206\u5e03\u5f0f\u4f17\u6838\u7cfb\u7edf\u3001\u4f4e\u529f\u8017\u548c\u9ad8\u80fd\u6548\u7535\u8def\u7cfb\u7edf\u3001\u7c7b\u8111\u7535\u8def\u548c\u7cfb\u7edf\u7b49\u65b9\u9762\u53d1\u6325\u7740\u91cd\u8981\u4f5c\u7528\u3002\u751f\u7269\u7cfb\u7edf\u9664\u4e86\u5929\u7136\u5730\u4ee5\u4e8b\u4ef6\u9a71\u52a8\u548c\u5f02\u6b65\u65b9\u5f0f\u8fdb\u884c\u8ba1\u7b97\u4e4b\u5916\uff0c\u5176\u7279\u6027\u548c\u65f6\u95f4\u52a8\u6001\u5bc6\u5207\u76f8\u5173\uff0c\u6a21\u62df\u771f\u5b9e\u795e\u7ecf\u5143\u548c\u7a81\u89e6\u7684\u6df7\u5408\u6a21\u62df\/\u6570\u5b57\u786c\u4ef6\u67b6\u6784\u4ee3\u8868\u4e86\u4e00\u79cd\u6709\u524d\u666f\u7684\u6280\u672f\uff0c\u6210\u4e3a\u4e86\u5b66\u672f\u53ca\u5de5\u4e1a\u754c\u5171\u540c\u7684\u5c55\u671b\u65b9\u5411\u3002<\/p>\n

\"\"<\/p>\n

\"\"<\/strong><\/p>\n

\u4eae\u70b9\u524d\u77bb1<\/strong><\/p>\n

\u4e3b\u65e8\u62a5\u544a<\/strong><\/p>\n

Mike Davies<\/strong><\/p>\n

\"\"<\/p>\n

Neuromorphic Computing<\/p>\n

Laboratory, Intel Corporation<\/p>\n

Title: Go Big or Go Home<\/strong><\/p>\n

Abstract: After decades of research and a handful of commercial applications, asynchronous design remains a niche methodology at the fringe of the semiconductor industry. The reasons for this are well known: lack of EDA tool support, lack of standardization, limited literature quantifying sync-versus-async tradeoffs, and a \u201cblack art\u201d reputation with little mainstream awareness. Asynchronous circuits can outperform synchronous circuits, but in most cases the gains are insufficient to overcome the costs of deviating from standard synchronous methods. For this to change and for asynchronous design to thrive, a compelling killer app is needed \u2013 a new class of computing device in which the benefits of asynchrony overwhelm the cost of synchronization at the circuit level. Biological neural circuits in the brains of animals have that characteristic, perhaps the only known example. In this talk I will describe the deep synergies between asynchronous design and neuromorphic chips inspired by biological neural networks. Arguably the fates of these two technologies are fundamentally.<\/p>\n

Giacomo INDIVERI<\/strong><\/p>\n

\"\"<\/p>\n

University of Zurich and ETH Zurich, Switzerland<\/p>\n

Title: Brain-inspired routing in mixed-signal neuromorphic processor<\/strong><\/p>\n

For many edge-computing tasks that require real-time processing of sensory data and closed-loop interactions with the environment, conventional ANN accelerators cannot match the performance and efficiency of animal brains. One of the reasons for this gap is that neural computation in biological systems is organized in a way that is very different from the way it is implemented in today’s deep network accelerators. In addition to being naturally event driven and asynchronous, neural computation in biological systems is tightly linked to the physics of their computing elements and to their temporal dynamics. Mixed-signal brain-inspired hardware architectures that emulate the biophysics of real neurons and synapses represent a promising technology for implementing alternative computing paradigms that bridge this gap.In this talk I will present hybrid analog\/digital electronic circuits that directly emulate the biophysics of neural systems and present brain-inspired routing schemes multi-core architectures that support small-world network connectivity and minimize memory requirements.<\/p>\n

Yvain Thonnart<\/strong><\/p>\n

\"\"<\/p>\n

CEA-List, France<\/p>\n

Title: The ANOC Asynchronous Communication Architecture: a Retrospective on a 15-year Circuit Roadmap<\/strong><\/p>\n

Kanwen(Kevin) Wang<\/strong><\/p>\n

\"\"<\/p>\n

Huawei Technologies Co., Ltd., China<\/p>\n

Title:Our Practice and Expectations on Asynchronous Design<\/strong><\/p>\n

 <\/p>\n

\u4eae\u70b9\u524d\u77bb2\u00a0<\/strong><\/p>\n

Special Session<\/strong><\/p>\n

Huaqiang Wu<\/strong><\/p>\n

Tsinghua University,China<\/p>\n

Title: Memristor-based Energy-Efficient Neuromorphic Computing<\/p>\n

Elisabetta Chicca<\/strong><\/p>\n

University of Groningen, The Netherlands<\/p>\n

Title: Biologically Realistic Learning in Full Custom CMOS Asynchronous Systems<\/p>\n

Gang Pan<\/strong><\/p>\n

Zhejiang University<\/p>\n

Title: Neuromorphic Computer: Progresses, Challenges, and Practices<\/p>\n

Tutorial<\/strong><\/p>\n

Rajit Manohar\u00a0<\/strong><\/p>\n

Computer Systems Lab at Yale, USA<\/p>\n

Title: An ASIC Flow for Asynchronous Logic<\/p>\n

 <\/p>\n

\u4eae\u70b9\u524d\u77bb3<\/strong><\/p>\n

Session: Asynchronous Pipelines, Architectures, CPUs, and Circuits<\/strong><\/p>\n

\"\"<\/strong><\/a><\/p>\n

A Smart Event-based Vision Sensor with a 320K Neuron Convolutional Neuronal Network Processing Pipeline<\/strong><\/a><\/p>\n

The nature of event-driven sensing and computing facilitates the development of lightweight, standalone AI applications with exceptionally low latency and a minimal power consumption. This paper presents a demonstration of an end-to-end, fully event-driven spiking neural network (SNN) inference using a smart vision System on Chip (SoC) called Speck\u2122. Speck\u2122, the world’s first neuromorphic chip, integrates a dynamic vision sensor and an SNN ASIC on a single die. In this paper, we demonstrate that Speck\u2122 is highly optimized for loaded SNN and event-based vision signals, enabling effective handling of various real-life vision tasks by leveraging its asynchronous structure. Moreover, we showcase our comprehensive neuromorphic software pipeline, which significantly simplifies the development of neuromorphic applications based on Speck\u2122.<\/p>\n

\u4fe1\u606f\u53ca\u56fe\u7247\u6765\u6e90\uff1aASYNC\u3001\u4e9a\u6602\u5b66\u672f<\/p>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

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